Implementing compilers since 1975.
Broad and deep experience in the design and implementation of compilers for a variety of programming languages including Ada, BLISS, C, C++, COBOL, Fortran, Lisp, Modula-2, Pascal, Perl, PL/1, PL/SQL SQL, Verilog, VHDL.
Areas of Expertise
Parsing
Experienced with LALR and LL parsers as well as recursive descent. Extended existing grammars with context-sensitive keywords. Implemented a single YACC parser handling multiple variant SQL grammar variations.
GNU TOOL CHAIN
A variety of porting work, including adding 8-bit character support to a non-byte addressable DSP, maintaining and enhancing the GCC ARM port for additional instructions and addressing modes.
Cross compiler tool chains for a variety of architectures such as:
8 bit IOT chip with banked memory addressing
32 bit network router with 512 registers and no memory
32 bit NAS protocol engine
32/64 bit super-computer on a chip (64 cores/chip with high speed crossbar interconnects)
32 bit mult-icore, multi-threaded network router/wifi controller. Chip is used in a wide range of commercial and home network products from multiple OEMs
Typical tool chains include simulator, assembler, linker, GNU debugger,compilers for C, C++ and POSIX-compliant libraries.
OPTIMIZATION
Common data-flow analysis shared by Pascal, C, Fortran and Modula compilers including loop-invariance, DU/UD chains, disjoint variable lifetimes.
Aggressive constant folding for VHDL/Verilog using BDD/SAT.
Tree transformation with syntax-directed translation via inherited and synthesized attributes.
TECHNOLOGY ASSESSMENT
Neutral due-diligence evaluation of technology for HP's purchase of Windows RPC software technology from source-code vendor.
Assessment of clean room Java implementations as to suitability for realtime system vendor.
Authored white paper positioning source-control and configuration management tools for ISO 9000.
INSTRUCTION SELECTION
Instruction selection using a variety of techniques, including pattern recognition, tiling, best-fit.
Register assignment as bin-packing, split lifetime allocation.
HardWARE DeSIGN
Participation in HW architecture design to enhance high-level language support and efficient code generation, including advice on addressing modes, stack operations, branch logic, delay-slot behavior.
RunTIME Libraries
Assembly-language routines for DSP runtime. porting libc,writing runtime libraries for PL/1 PICTURE formatting, simulation of IBM COBOL decimal conversions (packed, zoned, etc).
“Good, Fast, Cheap. Pick any two.”